TCA6416A Datasheet, PDF (14/32 Pages) Texas Instruments – LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

TCA6416A
SCPS194 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com
I²C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
f_scl
t_sch
t_scl
t_sp
t_sds
t_sdh
t_icr
t_icf
t_ocf
t_buf
t_sts
t_sth
t_sps
t_vd(data)
t_vd(ack)
I²C clock frequency
I²C clock high time
I²C clock low time
I²C spike time
I²C serial data setup time
I²C serial data hold time
I²C input rise time
I²C input fall time
I²C output fall time; 10 pF to 400 pF bus
I²C bus free time between Stop and Start
I²C Start or repeater Start condition setup time
I²C Start or repeater Start condition hold time
I²C Stop condition setup time
Valid data time; SCL low to SDA output valid
Valid data time of ACK condition; ACK signal from SCL low to SDA
(out) low
STANDARD MODE
I²C BUS
MIN
MAX
0
100
4
4.7
0
50
250
0
1000
300
300
4.7
4.7
4
4
1
1
FAST MODE
I²C BUS
MIN
MAX
0
400
0.6
1.3
0
50
100
0
20 + 0.1C_b(1)
300
20 + 0.1C_b(1)
300
20 + 0.1C_b(1)
300
1.3
0.6
0.6
0.6
1
UNIT
kHz
µs
µs
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
1 µs
(1) C_b = total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
t_W
t_REC
t_RESET
Reset pulse duration
Reset recovery time
Time to reset⁽¹⁾
FAST MODE
I²C BUS
STANDARD MODE
I²C BUS
MIN
MAX
MIN
4
4
0
0
600
600
(1) Minimum time for SDA to become high or minimum time to wait before doing a START
MAX
UNIT
ns
ns
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, C_L ≤ 100 pF (unless otherwise noted) (see Figure 10)
PARAMETER
FROM
FAST MODE
I²C BUTSO
STANDARD MODE
I²C BUS
MIN
MAX
UNIT
MIN
MAX
t_IV
Interrupt valid time
t_IR
Interrupt reset delay time
t_PV Output data valid
t_PS Input data setup time
t_PH Input data hold time
P port
SCL
SCL
P port
P port
INT
INT
P7–P0
SCL
SCL
4
4 µs
4
4 µs
400
400 ns
0
0
ns
300
300
ns
14
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