SN75DP120 Datasheet, PDF (9/27 Pages) Texas Instruments – DisplayPort 1:1 Dual-Mode Repeater

SN75DP120
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I_CC
Supply current under active operating LP# = VCC, ML: VOD = 1200mVp-p,
mode
2.7Gbps PRBS; AUX: VID = 1000mVp-p,
1Mbps PRBS; VDD= 3.6V, VCC=3.6V
I_PDWN
Device power under power down
mode (D3) or standby main link
disabled
LP# = VCC, ML: VID = 0mVp-p,
AUX: VID = 0mVp-p; VDD= 3.6V, VCC=3.6V
Low power current
I_LP
LP# = 0V, VDD= 3.6V, VCC=3.6V HPD_INV,
CAD_INV = NC, 0V
LP# = 0V, VDD= 3.6V, VCC=3.6V
HPD_INV=VCC
I_DD
t_PWDNEX
Supply current
D3 Powerdown or standby mode exit
time
VDD = 3.6V, HPD_INV = VDD
Total time for the device to exit from D3 or standby
state to active mode
SLLSE08 – OCTOBER 2009
MIN TYP MAX UNIT
165 200 mA
8
12 mA
1
10 µA
400 640
4 mA
1.2 1.8 µs
HOT PLUG AND CABLE ADAPTER DETECT
The SN75DP120 has an integrated 125KΩ pull down on the HPD_SINK input pin. The HPD and CAD timing
diagrams in this section are for the non-inverting case. The same timing diagrams apply for the inverting case
except the output is inverted. The VOH level of CAD_SRC follows that of VDD irrespective of CAD_INV setting.
However VOH for HPD_SRC depends on HPD_INV setting. When HPD_INV is low or left floating, HPD_SRC
VOH follows that of VDD. When HPD_INV = H then HPD_SRC VOH is set to 0.8V – 1.1V irrespective of VDD.
Explanation of HPD power management and interrupt behavior of the SN75DP120 is located in the Application
Information section at the end of the datasheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
HPD_INV, CAD_INV = L
V_OH3.3
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 3.3 V, I_OH = –100 µA,
CAD_SINK, HPD_SINK = H
V_OH2.5
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 2.5 V, I_OH = –100 µA,
CAD_SINK, HPD_SINK = H
V_OH1.8
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 1.8 V, I_OH = –100 µA,
CAD_SINK, HPD_SINK = H
V_OL3.3
High-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 3.3 V, I_OL = 100 µA,
CAD_SINK, HPD_SINK = L
V_OL2.5
Low-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 2.5 V, I_OL = 100 µA,
CAD_SINK, HPD_SINK = L
V_OL1.8
Low-level output voltage
(CAD_SRC and HPD_SRC)
VDD = 1.8 V, I_OL = 100 µA,
CAD_SINK, HPD_SINK = L
HPD_INV = H
V_OH1.1
High-level output voltage
(HPD_SRC)
I_OH = –100 µA,
HPD_SINK = L
V_OL1.1
Low-level output voltage
(HPD_SRC)
I_OH = 100 µA,
HPD_SINK = H
I_IH
I_L
R_HPDIN
High-level input current
(HPD_SINK, CAD_SINK, HPD_INV, CAD_INV)
lLow-level input current
(HPD_SINK, CAD_SINK, HPD_INV, CAD_INV)
Weak pull down resistor on HPD_SINK
V_IH = 2.0 V, V_DD = 3.6 V
(Leakage includes pull down resistor)
V_IL = 0.8 V, V_DD = 3.6 V
(Leakage includes pull down resistor)
MIN TYP MAX UNIT
3
V
2.25
V
1.62
1.8 V
0.1 V
0.1 V
0.1 V
0.8 0.9 1.1 V
0.1 V
–5
35 µA
–5
35 µA
100 125 150 kΩ
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN75DP120
Submit Documentation Feedback
9