SN75DP120 Datasheet, PDF (11/27 Pages) Texas Instruments – DisplayPort 1:1 Dual-Mode Repeater

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HPD_SINK
V_CC
SN75DP120
SLLSE08 – OCTOBER 2009
0V
V_DD ^{HPD _SRC}
Sink Hot Plug Detect
Timeout
t _T(HPD)
0V
Active
Standby
Figure 4. HPD Timing Diagram #2 (HPD_INV = L)
CAD _ SINK
V_CC
50%
0V
tPD(CAD)
V_CC ^{CAD_ SRC}
50%
tPD(CAD)
0V
Figure 5. CAD Timing Diagram
DisplayPort Auxiliary Pins
The SN75DP120 is designed to monitor the bidirectional auxiliary signals in DP mode and participates in link
training. The SN75DP120 adjusts the output swing, output pre-emphasis, and the EQ setting of every main link
port. The SN75DP120 AUX monitor configures the output based on the DPCD addresses below.
The AUX channel is monitored for the Display Port D3 standby command. Upon detecting the D3 command, the
SN75DP120 will go into a low power standby state with the AUX activity monitor remaining active.
ADDRESS
00100h
00101h
NAME
LINK_BW_SET
LANE_COUNT_SET
Table 3. DPCD Lookup Table
DESCRIPTION
Main Link Bandwidth Setting
Bits 7:0 = link bandwidth setting
● 06h = 1.62Gbps per lane (default)
● 0Ah = 2.7Gbps per lane
Note: Setting the register value in register 0100h to anything else but 0Ah puts the device into
1.62Gbps mode.
Determines the number of lanes to be enabled
Bits 4:0 = lane count
● 1h = one lane
● 2h = two lanes
● 4h = four lanes
Note: Any other register value in register 0101h bit 4:0 is invalid and disables all OUTx lanes until
the register value is changed back to a valid entry. Default all lanes are disabled.
Copyright © 2009, Texas Instruments Incorporated
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