SN74LVCE161284 Datasheet, PDF (9/14 Pages) Texas Instruments – 19 BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR FREE POWER UP

SN74LVCE161284
19ĆBIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERRORĆFREE POWER UP
SCES541 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
From
B or Y Output
Under Test
VCC CABLE
62 Ω
CL = 50 pF
(see Note A)
TP1
Sink Load
Source Load
62 Ω
CL = 50 pF
(see Note A)
Input
(see Note B)
2.7 V
0V
tf1
Output
(see Note B)
95% (VCC CABLE = 5.0 V"0.5 V)
50% (VCC CABLE = 5.0 V"0.5 V)
tr1
Output
(see Note B)
1.9 V (VCC CABLE = 5.0 V"0.5 V)
0.4 V
VOLTAGE WAVEFORMS MEASURED AT TP1
SLEW RATE WAVEFORMS (B1−8 AND Y9−13)
SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT
VCC CABLE
TP1
From
B or Y Output
500 Ω
CL = 50 pF
(see Note A)
Input
(see Note C)
1.4 V
1.4 V
2.7 V
0V
Output
(see Note C)
2V
0.8 V
tr
2V
0.8 V
tf
VOH
VOL
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN) OR PERI LOGIC IN TO PERI LOGIC OUT
NOTES: A. CL includes probe and jig capacitance.
B. When VCC CABLE is 3.3 V " 0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and
1.9 V for the falling edge. When VCC CABLE is 5 V " 0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge
and between 95% VCC CABLE and 50% VCC CABLE for the falling edge.
ǒ Ǔ t_slew fall + V_CC
95% – 50%
t_f1
ǒ Ǔ t_slew rise +
1.9 V – 0.4 V
t_r1
C. Input rise (tr) and fall (tf) times are 3 ns. Rise and fall times (open drain) are <120 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuits and Voltage Waveforms
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