SN74LVCE161284 Datasheet, PDF (10/14 Pages) Texas Instruments – 19 BIT IEEE 1284 TRANSLATION TRANSCEIVER WITH ERROR FREE POWER UP

SN74LVCE161284
19ĆBIT IEEE 1284 TRANSLATION TRANSCEIVER
WITH ERRORĆFREE POWER UP
SCES541 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
VCC × 2 V When Measuring the Cable Side, VCC CABLE × 2 V
S1
Open
TEST
S1
GND
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VCC × 2 V
GND
LOAD CIRCUIT
Input
(see Note B)
1.4 V
1.4 V
2.7 V
0V
tPLH
tPHL
VOH
Output
50% VCC
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
Output
Control
1.4 V
1.4 V
2.7 V
0V
Output
Waveform 1
S1 at VCC × 2 V
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
tPZL
tPZH
1.4 V
tPLZ
VOH
VOL + 0.3 V _VOL
tPHZ
1.4 V
VOH − 0.3 V ^VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
HOST LOGIC IN TO HOST LOGIC OUT OR B-TO-A LOAD (TOTEM POLE)
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
LOAD CIRCUIT
VCC CABLE × 2 V
Open
GND
Input
(see Note D)
tPLH
Output
TEST
tPLH
tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VCC CABLE × 2 V
VCC CABLE × 2 V
GND
tw
1.4 V
VOL + 1.4 V
1.4 V
2.7 V
0V
tPHL
VOH
VOH − 1.4 V
VOL
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
A-TO-B LOAD OR A-TO-Y LOAD (TOTEM POLE) OR PERI LOGIC IN TO PERI LOGIC OUT
NOTES: A. CL includes probe and jig capacitance.
B. Input rise and fall times are 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < tw < 10 µs.
E. The outputs are measured one at a time, with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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