MSP430FG42X0 Datasheet, PDF (9/65 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430FG42x0 Configuration
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out-of-Range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
0FFFCh
14
(Non)maskable
0FFFAh
13
SD16_A
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
0FFF8h
12
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
0FFF2h
9
0FFF0h
8
0FFEEh
7
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
4
DAC12
DAC12_0IFG
(see Note 2)
Maskable
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h 0, lowest
NOTES:
1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges (MSP430FG4270, MSP430FG4260: from 0300h to 0BFFh and from 01100h to 07FFFh,
MSP430FG4250: from 0300h to 0BFFh and from 01100h to 0BFFFh).
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