BQ24747 Datasheet, PDF (9/36 Pages) Texas Instruments – SMBus-Controlled Level 2 Multi-Chemistry Battery Charger With Input Current Detect Comparator and Charge Enable Pin

bq24747
www.ti.com ............................................................................................................................................................................................. SLUS988 – OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ V(DCIN) ≤ 24 V, 0°C < T_J < +125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDDSMB INPUT SUPPLY FOR SMBus
V_{VDDSMB_RANGE}
V_{VDDSMB_UVLO_}
Threshold_Rising
V_{VDDSMB_UVLO_}
Hyst_Rising
IVDDSMB_Iq
VDDSMB input voltage range
VDDSMB undervoltage lockout threshold
voltage, rising
VDDSMB undervoltage lockout hysteresis
voltage, falling
VDDSMB quiescent current
V_VDDSMB Rising
V_VDDSMB Falling
V_VDDSMB = SCL = SDA = 5.5 V,
0°C ≤ T_J ≤ 85°C
2.7
5.5
V
2.4
2.5
2.65
V
100
150
200 mV
20
27 μA
ELECTRICAL CHARACTERISTICS
7 Vdc ≤ V_(VCC) ≤ 24 Vdc, –20°C<T_J <125°C, ref = AGND (unless otherwise noted)⁽¹⁾
PARAMETER
[SMB TIMING SPECIFICATION (VDD = 2.7 V to 5.5 V) (see Figures 4 and 5)]
MIN TYP MAX UNIT
SMBus TIMING CHARACTERISTICS
t_R
SCLK/SDATA rise time
t_F
SCLK/SDATA fall time
t_W(H)
SCLK pulse width high
t_W(L)
SCLK Pulse Width Low
t_SU(STA)
Setup time for START condition
t_H(STA)
START condition hold time after which first clock pulse is generated
t_SU(DAT)
Data setup time
t_H(DAT)
Data hold time
t_SU(STOP) Setup time for STOP condition
t_(BUF)
Bus free time between START and STOP condition
F_S(CL)
Clock Frequency
HOST COMMUNICATION FAILURE
1 μs
300 ns
4
50 μs
4.7
μs
4.7
μs
4
μs
250
ns
300
ns
4
μs
4.7
μs
10
100 kHz
t_timeout
SMBus bus release timeout
t_WDI
Watchdog timeout period
OUTPUT BUFFER CHARACTERISTICS
22 25 35 ms
140 170 210
s
V_(SDAL)
Output LO voltage at SDA, I_(SDA) = 3 mA
0.4 V
(1) Devices participating in a transfer will timeout when any clock low exceeds the 25 ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a
slave (25 ms).
Copyright © 2009, Texas Instruments Incorporated
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