AFE8406IZDQ Datasheet, PDF (9/151 Pages) Texas Instruments – 14-BIT, 85 MSPS DUAL ADC, 8-CHANNEL WIDEBAND RECEIVER

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AFE8406
14-BIT, 85 MSPS DUAL ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS168C – MAY 2005 – REVISED OCTOBER 2008
T_A = –40°C to 85°C (unless otherwise noted)
PARAMETER
t_CHD
t_CSPW
t_CDLY
t_REC
t_HIZ
t_COH
Control hold during writes.
3 pin mode: a[5:0] and d[15:0] valid after wr_n and ce_n rise
2 pin mode: a[5:0], d[15:0] and wr_n valid after ce_n rise ⁽²⁾
Control strobe (ce_n and wr_n low) pulse duration during write. ⁽²⁾
Control output delay ce_n and rd_n low and a[5:0] stable to d[15:0] during read. ⁽²⁾
Control recovery time between reads or writes. ⁽²⁾
Control end of read to Hi-Z. rd_n and ce_n rise to d[15:0] 3-state ⁽⁴⁾
Control read d[15:0] output hold time
(4) Specified by design and process, and not directly tested.
MIN TYP MAX UNIT
6
ns
25
ns
25 ns
6 ns
10 ns
1
ns
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SPECIFICATIONS
9