AFE8406IZDQ Datasheet, PDF (143/151 Pages) Texas Instruments – 14-BIT, 85 MSPS DUAL ADC, 8-CHANNEL WIDEBAND RECEIVER

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AFE8406
14-BIT, 85 MSPS DUAL ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS168C – MAY 2005 – REVISED OCTOBER 2008
When muxed_data is set (Factory Use Only) rate_sel should be set to rxclk “00” and ch_rate_sel should
be set to rxclk/2 “01”.
remix_only : Assert this when real only, full rxclk rate input data is used in CDMA mode. The signal on the
Q bus selected by the ddcmux_sel_X(3:0) bits above is ignored (functions as if the Q data is
0).
cic_bypass : Factory Use Only. If asserted then the data from the rxin_a(15:0) and rxin_b(15:0) are fed
directly into the cfir input as I and Q respectively. rxin_a(0) also functions as the “sync_cfir”
signal and should rise at the beginning of input data.
ONLY DDC0, DDC2, DDC4 and DDC6 can be the UMTS double tap (64 to 128 tap) PFIR Mode.
DDC1, DDC3, DDC5 and DDC7 PFIRs are used to lengthen the DDC0, DDC2, DDC4 and DDC6
PFIRs.
double_tap(1) : When set, the DDC is in double length PFIR mode which sends the data out of the last
PFIR sample ram in this DDC (DDC0, DDC2, DDC4, DDC6) to the adjacent secondary DDC
(DDC1, DDC3, DDC5, DDC7) PFIR forming a 128-tap delay line. Output data received from
the adjacent secondary DDC PFIR summer is added into the Main DDC’s PFIR sum to form
the final output.
double_tap(0) : When set, the PFIR input comes from the adjacent(Main) PFIR. When cleared, PFIR input
is from the CFIR connected directly to this PFIR. Only valid in DDC1, DDC3, DDC5 and
DDC7. The ddc_ena bit in the CONFIG1 register should be cleared for the DDC1,
DDC3, DDC5 and DDC7 when double_tap(0) is set.
NOTE: to put 2 DDCs in to 128 tap mode:
Program DDC0/DDC2/DDC4/DDC6 double_tap(1:0) to “10” and ddc_ena to “1”.
Program DDC1/DDC3/DDC5/DDC7 double_tap(1:0) to “01” and ddc_ena to “0”.
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AFE8406 GENERAL CONTROL 143