XIO2001 Datasheet, PDF (85/131 Pages) Texas Instruments – Express™ to PCI Bus Translation Bridge

www.ti.com
XIO2001 PCI Express™ to PCI Bus Translation Bridge
SCPS212B – MAY 2009 – REVISED JULY 2009
4.68 Clock Run Status Register
The clock run status register indicates the state of the PCI clock-run features in the bridge. See
Table 4-42 for a complete description of the register contents.
PCI register offset: DAh
Register type:
Read-only
Default value:
00h
BIT NUMBER
RESET STATE
76543210
00000000
Table 4-42. Clock Run Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
7:1 RSVD
R
Reserved. Returns 000 0000b when read.
0⁽¹⁾
Secondary clock status. This bit indicates the status of the PCI bus secondary clock
outputs.
SEC_CLK_STATUS
RU
0 = Secondary clock running
1 = Secondary clock stopped
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Submit Documentation Feedback
Classic PCI Configuration Space
85