XIO2001 Datasheet, PDF (114/131 Pages) Texas Instruments – Express™ to PCI Bus Translation Bridge

XIO2001 PCI Express™ to PCI Bus Translation Bridge
SCPS212B – MAY 2009 – REVISED JULY 2009
Table 6-7. Serial IRQ Edge Control Register Description (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
3⁽¹⁾ IRQ3_MODE
IRQ 3 edge mode
RW
0 = Edge mode (default)
1 = Level mode
2⁽¹⁾ IRQ2_MODE
IRQ 2 edge mode
RW
0 = Edge mode (default)
1 = Level mode
1⁽¹⁾ IRQ1_MODE
IRQ 1 edge mode
RW
0 = Edge mode (default)
1 = Level mode
0⁽¹⁾ IRQ0_MODE
IRQ 0 edge mode
RW
0 = Edge mode (default)
1 = Level mode
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6.11 Serial IRQ Status Register
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode
IRQ is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that
are defined as edge mode in the serial IRQ edge control register are not reported in this status register.
This register is an alias for the serial IRQ status register in the classic PCI configuration space (offset E4h,
see Section 4.74). See Table 4-48 for a complete description of the register contents.
Device control memory window register 4Ch
offset:
Register type:
Read/Clear
Default value:
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
FIELD NAME
15⁽¹⁾ IRQ15
14⁽¹⁾ IRQ14
13⁽¹⁾ IRQ13
Table 6-8. Serial IRQ Status Register Description
ACCESS
DESCRIPTION
RCU
IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted.
0 = Deasserted
1 = Asserted
RCU
IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted.
0 = Deasserted
1 = Asserted
RCU
IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.
0 = Deasserted
1 = Asserted
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
114 Memory-Mapped TI Proprietary Register Space
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