TMS320F2812 Datasheet, PDF (81/103 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
serial communications interface (SCI) module (continued)
Figure 19 shows the SCI module block diagram.
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
Frame Format and Mode
Parity
Even/Odd Enable
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
SCIHBAUD. 15 – 8
LSPCLK
Baud Rate
MSbyte
Register
SCILBAUD. 7 – 0
Baud Rate
LSbyte
Register
SCIRXST.7 SCIRXST.4 – 2
RX Error
FE OE PE
RX Error
TXSHF
Register
8
Transmitter–Data
Buffer Register
8
TX FIFO _0
TX FIFO _1
–––––
TX FIFO _15
SCITXBUF.7–0
TX FIFO registers
SCIFFENA
SCIFFTX.14
SCICTL1.1
TXENA
TX EMPTY
SCICTL2.6
TXRDY
SCICTL2.7
SCITXD
TX INT ENA
SCICTL2.0
TX FIFO Interrupt
TX Interrupt
Logic
SCI TX Interrupt select logic
AutoBaud Detect logic
RXSHF
Register
RXENA
8 ^SCICTL1.0
SCIRXD
RXWAKE
SCIRXST.1
Receive Data
Buffer register
SCIRXBUF.7–0
8
RX FIFO _15
–––––
RX FIFO_1
RX FIFO _0
SCIRXBUF.7–0
RX FIFO registers
RXFFOVF
SCIFFRX.15
SCICTL2.1
RXRDY RX/BK INT ENA
SCIRXST.6
BRKDT
SCIRXST.5
RX FIFO Interrupt
RX Interrupt
Logic
TXINT
To CPU
RXINT
To CPU
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
SCITXD
SCIRXD
Figure 19. Serial Communications Interface (SCI) Module Block Diagram
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