TMS320F2812 Datasheet, PDF (76/103 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
multichannel buffered serial port (McBSP) module (continued)
Figure 18 shows the block diagram of the McBSP module with FIFO, interfaced to the F2810 and F2812 version
of Peripheral Frame 2.
Peripheral Write Bus
MXINT
To CPU
LSPCLK
TX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
McBSP Registers and
Control Logic
TX FIFO
Interrupt
TX FIFO _15
TX FIFO _15
—
—
TX FIFO _1
TX FIFO _1
TX FIFO _0
TX FIFO _0
TX FIFO Registers
16
16
DXR2 Transmit Buffer
16
XSR2
DXR1 Transmit Buffer
16
Compand Logic
XSR1
McBSP
McBSP Receive
Interrupt Select Logic
MRINT
To CPU
RX Interrupt Logic
RSR2
16
RBR2 Register
16
RSR1
16
Expand Logic
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
16
16
RX FIFO
Interrupt
RX FIFO _15
—
RX FIFO _15
—
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
FSX
CLKX
DX
DR
CLKR
FSR
Figure 18. McBSP Module With FIFO
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