XIO3130_0808 Datasheet, PDF (80/139 Pages) Texas Instruments – XIO3130 switch is a PCI Express ´1 3-port fanout switch

XIO3130
SLLS693D – MAY 2007 – REVISED AUGUST 2008
www.ti.com
4.2.76 Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express Advanced Error
Reporting Capabilities. The register returns 0001h when read.
PCI register offset:
100h
Register type:
Read only
Default value:
0001h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4.2.77 Next Capability Offset/Capability Version Register
This read-only register returns the value 0000h to indicate that this extended capability block represents
the end of the linked list of extended capability structures. The least significant four bits identify the
revision of the current capability block as 1h.
PCI register offset:
102h
Register type:
Read only
Default value:
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.78 Uncorrectable Error Status Register
This register reports the status of individual errors as they occur. Software may clear these bits only by
writing a 1 to the desired location.
PCI register offset:
104h
Register type:
Read Only, Cleared by a Write of one
Default value:
0000 0000h
BIT NUMBER
RESET STATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
31:21
20
19
18
17
16
15
14
13
FIELD NAME
RSVD
UR_ERROR
ECRC_ERROR
MAL_TLP
RX_OVERFLOW
UNXP_CPL
CPL_ABORT
CPL_TIMEOUT
FC_ERROR
Table 4-44. Uncorrectable Error Status Register
ACCESS
r
rcuh
rcuh
rcuh
rcuh
rcuh
rcuh
rcuh
rcuh
DESCRIPTION
Reserved. Return zeros when read.
Unsupported Request error. This bit is asserted when an Unsupported Request error is
detected (i.e., when a request is received that results in the sending of a completion with
an Unsupported Request status).
Extended CRC error. This bit is asserted when an Extended CRC error is detected.
Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver overflow. This bit is asserted when the flow control logic detects that the
transmitting device has illegally exceeded the number of credits that were issued.
Unexpected completion. This bit is asserted when a completion packet is received that
does not correspond to an issued request.
Completer abort. This bit is asserted when the completion to a pending request arrives with
Completer Abort status.
Completion timeout. This bit is asserted when no completion has been received for an
issued request before the timeout period.
Flow control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
80
XIO3130 Configuration Register Space
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