XIO3130_0808 Datasheet, PDF (22/139 Pages) Texas Instruments – XIO3130 switch is a PCI Express ´1 3-port fanout switch

XIO3130
SLLS693D – MAY 2007 – REVISED AUGUST 2008
3 Description
Figure 3-1 is the block diagram of the XIO3130.
EEPROM
Clock
Distribution/
Reset Logic
PCI
Express
X1 Phy
Port 0
(Up)
Logic
Virtual
PCI to
PCI
Bridge
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GPIO
PCI Hot
Plug
Virtual
PCI to
PCI Bridge
Bridge
Port 1
(Down)
Logic
PCI
Express x1
Phy
Virtual
PCI to
PCI Bridge
Bridge
Port 2
(Down)
Logic
PCI
Express x1
Phy
Virtual
PCI to
PCI Bridge
Bridge
Port 3
(down)
logic
PCI
Express x1
Phy
Figure 3-1. Block Diagram
3.1 Power-Up/Power-Down Sequencing
The following sections describe the procedures to power up and power down the XIO3130 switch.
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages in any order with any time relationship and with any ramp rate.
3. Apply a stable PCI Express reference clock.
To meet PCI Express specification requirements, PERST cannot be de-asserted until the following two
delay requirements are satisfied:
• Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit
satisfies the requirement for stable device clocks by the de-assertion of PERST.
• Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the de-assertion of PERST.
See Figure 3-2, Power-Up Sequence Diagram.
22
Description
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