ADS5295 Datasheet, PDF (80/91 Pages) Texas Instruments – 12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter

ADS5295
SBAS595 – DECEMBER 2012
www.ti.com
PROGRAMMABLE LCLK PHASE
The ADS5295 enables the edge of the output bit clock (LCLK) to be programmed with the PHASE_DDR register
bits. The default value of PHASE_DDR after reset is '10'. The default phase is shown in Figure 72.
ADCLKP
LCLKP
DATA
OUT
PHASE_DDR[1:0] = 10
Figure 72. Default LCLK Phase
The phase can also be changed by changing the value of the PHASE_DDR[1:0] bits, as shown in Figure 73.
ADCLKP
ADCLKP
LCLKP
DATA
OUT
PHASE_DDR[1:0] = 10
LCLKP
DATA
OUT
PHASE_DDR[1:0] = 00
ADCLKP
LCLKP
DATA
OUT
ADCLKP
LCLKP
DATA
OUT
PHASE_DDR[1:0] = 11
Figure 73. Programmable LCLK Phases
PHASE_DDR[1:0] = 01
80
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