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TS3L500AE_08 Datasheet, PDF (8/17 Pages) Texas Instruments – 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LED SWITCH AND ENHANCED ESD PROTECTION
TS3L500AE
SCDS246A – JUNE 2007 – REVISED AUGUST 2008 ....................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
Input Generator
50 Ω
VG1
Input Generator
50 Ω
VG2
VIN
50 Ω
VI
50 Ω
VCC
DUT
TEST CIRCUIT
VO
CL
(see Note A)
RL
RL
2 × VCC
S1
Open
GND
TEST
tPLZ/tPZL
tPHZ/tPZH
VCC
3.3 V ± 0.3 V
3.3 V ± 0.3 V
S1
2 × VCC
GND
RL
200 Ω
200 Ω
Vin
GND
VCC
CL
10 pF
10 pF
V∆
0.3 V
0.3 V
Output Control
VI
(VIN)
1.25 V
1.25 V
2.5 V
0V
tPZL
Output
Waveform 1
VO
S1 at 2 y VCC
(see Note B)
tPZH
Output
Waveform 2
VO
S1 at GND
(see Note B)
VCC/2
VCC/2
tPLZ
VOH
VOL + 0.3 V
tPHZ
VOH − 0.3 V
VOL
VOH
VOL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 5. Test Circuit and Voltage Waveforms
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