TPS54380PWPG4 Datasheet, PDF (8/21 Pages) Texas Instruments – 3-V TO 6-V INPUT, 3-A OUTPUT TRACKING SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FOR SEQUENCING

TPS54380
SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005
www.ti.com
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical
TPS54380 application. The TPS54380 (U1) can provide
greater than 3 A of output current at a nominal output
voltage of 1.8 V. For proper thermal performance, the
exposed thermal PowerPAD underneath the integrated
circuit package must be soldered to the printed-circuit
board. To provide power-up tracking, the enable of the I/O
supply should be used. If the I/O enable is not used to
power up, then devices with similar undervoltage lockout
thresholds need to be implemented to ensure power-up
tracking. To ensure power-down tracking, the enable pin
must be used.
TPS2013
Distribution Switch
VOUT_I/O
R4
10 kΩ
R6
9.76 kΩ
VIN
R2
71.5 kΩ
C2
1 µF
C6
C7
10 µF 10 µF
U1
20
RT
AGND ¹
19 _{ENA VSENSE} 2
18 _{TRACKIN COMP} 3
17 _{VBIAS PWRGD} 4
16 _VIN
BOOT ⁵
15 _VIN
PH ⁶
14 _VIN
7
PH
13 _PGND
PH ⁸
12 _PGND
11 _PGND
PH ⁹
PH ¹⁰
PwrPad
R1
10 kΩ
C5
0.047 µF
C1
R5
120 pF ^{7.15 kΩ}
C4
100 pF
R3
10 kΩ
R7
C3
768 Ω 820 pF
R8
9.76 kΩ
R9
2.4 Ω
L1
1 µH
C11
3300 pF
C8
C9 C10
22 µF 22 µF 22 µF
VOUT_CORE
C12
0.1 µF
Analog and Power Grounds are Tied at
the PowerPAD Under the Package of IC
Figure 9. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional design information is available
at www.ti.com.
at 1.8 V. R3, along with R7, R5, C1, C3, and C4 form the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.
OPERATING FREQUENCY
INPUT FILTER
The input voltage is a nominal 5 Vdc. The input filter C6 is
a 10-µF ceramic capacitor (Taiyo Yuden). C7, also a 10-µF
ceramic capacitor (Taiyo Yuden), provides high-frequency
decoupling of the TPS54380 from the input supply and
must be located as close as possible to the device. Ripple
current is carried in both C6 and C7, and the return path to
PGND must avoid the current circulating in the output
capacitors C8, C9, and C10.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R3 and R8 sets the output voltage for the circuit
In the application circuit, the 350-kHz operation is selected
by leaving RT open. Connecting a 180-kΩ to 68-kΩ
resistor between RT (pin 20) and analog ground can be
used to set the switching frequency from 280 kHz to 700
kHz. To calculate the RT resistor, use the following
equation:
R
+
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 1-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc resistance
(0.010 Ω) type, Vishay 1HLP2525CZ01. The capacitors
used are 22-µF, 6.3-V ceramic types with X5R dielectric.
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