TNETE100PMPGE Datasheet, PDF (8/26 Pages) Texas Instruments – SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLANE

ThunderLAN™ TNETE100
PCI ETHERNET™ CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN™
SPWS017B – APRIL 1995 – REVISED AUGUST 1996
Pin Functions (Continued)
PIN
TYPE†
NAME
NO.
DESCRIPTION
MEDIA-INDEPENDENT INTERFACE (100-Mbps CSMA / CD AND DEMAND PRIORITY) (CONTINUED)
MRXD0
MRXD1
MRXD2
MRXD3
Receive data. MRXD[3 : 0] is the nibble that receives data from the physical-media-dependent (PMD)
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front end. In demand-priority mode, ThunderLAN reads the frame priority of incoming frames on these
85
86
I
pins on the cycle before assertion of MRXDV (the cycle before frame reception begins).
• MRXD1 indicates the transmission priority of the received frame. A value of zero indicates
87
normal transmission, and a value of one indicates priority transmission.
Data on these pins is always synchronous to MRCLK.
MRXDV
89
I
Receive data valid. MRXDV indicates data on MRXD[3 : 0] is valid.
MRXER
90
I
Receive error. MRXER indicates reception of a coding error on received data.
MTCLK
71
I
Transmit clock. MTCLK is the transmit clock source from the attached PHY and PMI device.
MTXD0
MTXD1
MTXD2
MTXD3
Transmit data. MTXD[3 : 0] is the nibble that transmits data from TNETE100. When MTXEN is asserted,
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these pins carry data to be transmitted. In demand-priority mode, the TNETE100 drives the request
state of the adapter on these pins when MTXEN is not asserted (frame transmission not in progress).
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74
O
76
• MTXD0 asserted indicates the TNETE100 is requesting frame transmission.
• MTXD1 indicates the transmission priority required. A value of zero indicates normal
transmission, and a value of one indicates high-priority transmission.
Data on these pins is always synchronous to MTCLK.
MTXER
78
O
Transmit error. MTXER allows coding errors to be propagated across the MII.
MTXEN
77
O
Transmit enable. MTXEN indicates valid transmit data on MTXD[3 : 0].
NETWORK INTERFACE (10 Base-T AND AUI)
ACOLN
ACOLP
111
AUI receive pair. ACOLN and ACOLP are differential line receiver inputs and connect to receive pair
109
A
through transformer isolation, etc.
ARCVN
ARCVP
108
106
A
AUI receive pair. ARCVN and ARCVP are differential line receiver inputs and connect to receive pair
through transformer isolation, etc.
AXMTP
AXMTN
99
100
A
AUI transmit pair. AXMTP and AXMTN are differential line transmitter outputs.
FATEST
Analog test pin. FATEST provides access to the filter of the reference PLL. This pin should be left as
118
A
a “no connect.”
FIREF
116
A
Current reference. FIREF is used to set a current reference for the analog circuitry.
FONLY
120
A
Front-end only pin. When FONLY is tied high, all TNETE100 functions other than the on-chip front end
are disabled. The MII interface pins allow the PHY to be used as a stand-alone 10 Base-T front end.
FRCVN
FRCVP
105
103
A
10 Base-T receive pair. FRCVN and FRCVP are differential line receiver inputs and connect to receive
pair through transformer isolation, etc.
FXTL1
FXTL2
113
114
A
Crystal oscillator pins. Drive FXTL1 from a 20-MHz crystal oscillator module
FXMTP
FXMTN
97
98
A
† _{I = input, O = output, A = Analog}
10 Base-T transmit pair. FXMTP and FXMTN are differential line transmitter outputs.
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