TLV1570 Datasheet, PDF (8/28 Pages) Texas Instruments – 2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS SERIAL ANALOG-TO-DIGITAL CONVERTER

TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
initialization-software sequence (continued)
The TLV1570 interfaces to a DSP over five lines: CS, SCLK, SDOUT, SDIN, and FS, and interfaces to a µC over
four lines: CS, SCLK, SDOUT, and SDIN. The FS input should be pulled high in µC mode. The device is in 3-state
and power-down mode when CS is high. After CS falls, the TLV1570 checks the FS input at the CS falling edge
to determine the operation mode. If FS is low, DSP mode is set, otherwise µC mode is set.
TLV1570
TMS320
CS
SCLK
FS
SDIN
SDOUT
XF
CLKX
CLKR
FSX
FSR
DX
DR
Figure 3. DSP to TLV1570 Interface
TLV1570
CS
SCLK
µC
I/O Terminal
SCLK
FS
SDIN
SDOUT
DVDD
DX
DR
Figure 4. µC to TLV1570 Interface
grounding and decoupling considerations
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines (see Figure 5). This requires that the supply and reference pins be sufficiently
bypassed. In most cases 0.1 µF ceramic chip capacitors are adequate to keep the impedance low over a wide
frequency range. Since their effectiveness depends largely on the proximity to the individual supply pin. They
should be placed as close to the supply pins as possible.
To reduce high frequency and noise coupling, it is highly recommended that digital and analog ground be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND, under the package.
TLV1570
100 nF
DVDD _AVDD
DGND AGND
REF
100 nF
100 nF
Figure 5. Placement of Decoupling Capacitors
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