TLC5923 Datasheet, PDF (8/15 Pages) Texas Instruments – LED DRIVER

TLC5923
SLVS550 – DECEMBER 2004
www.ti.com
PRINCIPLES OF OPERATION (continued)
Dot correction data are entered for all channels at the same time. The complete dot correction data format
consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 9 shows the DC data format.
LSB
0
6
DC 0.0
DC 0.6
DC OUT0
7
DC 1.0
DC OUT2 − DC OUT14
104
105
MSB
111
DC 14.6 DC 15.0
DC 15.6
DC OUT15
Figure 9. DC Data Format
To input data into dot correction register, MODE must be set to high. The internal input shift register is then set to
112 bit width. After all serial data is clocked in, a rising edge of XLAT latch the data to the dot correction register
(Figure 13).
Output Enable
All OUTn channels of TLC5923 can switched off with one signal. When BLANK signal is set to high, all OUTn are
disabled, regardless of On/Off status of each OUTn. When BLANK is the to low, all OUTn work under normal
conditions.
Table 1. BLANK Signal Truth Table
BLANK
LOW
HIGH
OUT0 - OUT15
Normal condition
Disabled
Setting Channel On/Off Status
All OUTn channels of TLC5923 can be switched on or off independently. Each of the channels can be
programmed with a 1-bit word. On/Off data are entered for all channels at the same time. The complete On/Off
data format consists of 16 x 1-bit words, which form a 16-bit wide data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 10 shows the On/Off data format.
LSB
0
On/Off
OUT0
On/Off
OUT1
On/Off
OUT2
On/Off
OUT3
On/Off
OUT4
On/Off
OUT5
On/Off
OUT6
On/Off On/Off On/Off
OUT7 OUT8 OUT9
On/Off Data
On/Off
OUT10
On/Off
OUT11
On/Off
OUT12
On/Off
OUT13
On/Off
OUT14
MSB
15
On/Off
OUT15
Figure 10. On/Off Data
To input On/Off data into On/Off register MODE must be set to low. The internal input shift register is then set to
16 bit width. After all serial data is clocked in, a rising edge of XLAT during BLANK = high is used to latch data
into the On/Off register. Figure 13 shows the On/Off data input timing chart.
With the falling edge of XLAT signal all data in input shift register is replaced with LOD channel data. These data
is clocked out to SOUT when new On/Off data is clocked in.
Delay Between Outputs
The TLC5923 has graduated delay circuits between outputs. These delay circuits can be found in the constant
current block of the device (see Figure 1). The fixed delay time is 20 ns (typical), OUT0 has no delay, OUT1 has
20 ns delay, OUT2 has 40 ns delay, etc. This delay prevents large inrush currents, which reduce power supply
bypass capacitor requirements when the outputs turn on.
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