TLC5922 Datasheet, PDF(8/16 Page) Texas Instruments

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TLC5922 Datasheet, PDF (8/16 Pages) Texas Instruments – LED DRIVER

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TLC5922

SLVS486 â SEPTEMBER 2003

PRINCIPLES OF OPERATION (continued)

www.ti.com

SIN

SCLK

SOUT

XLAT

LAT

Figure 7. Shift Register and Data Latch for ON/OFF Setting

Delay Between Outputs

The TLC5922 has graduated delay circuits between outputs. In Figure 7, these delay circuits can be found

between OUTn and constant current block. The fixed delay time is 20 ns (TYP), OUT0 has no delay, OUT1 has

20 ns delay, OUT2 has 40 ns delay. This delay prevents large inrush currents, which reduce power supply

bypass capacitor requirements when the outputs turn on.

Setting Dot-Correction

The TLC5922 DC_LATCHn data latches hold the dot-correction information for each output. When the MODE

input is high, the processor can access both the DC_LATCHn and DC_REG registers. The 112 cascaded

DC_REG shift registers transfer dot-correction data from SIN to SOUT output at each rising edge of the SCLK

pin. XLAT is held low when the dot-correction data is clocked into the TLC5922. When all data is clocked in, the

rising edge of the XLAT pin transfers and latches the dot-correction data into the DC_LATCHn latches. Each of

the 16 DC_LATCHn data-latches holds a 7 bit digital code to adjust the constant current value for each of the 16

outputs. The processor must clock in 112 bits of data to fully program the dot-correction for all 16 channnels.

SIN D Q

SCLK

SOUT

XLAT

LAT

Bit 0 Bit 1 ââââ Bit 6

(LSB)

(MSB)

7[bit] Digital=>Analog

Bit 0 Bit 1 ââââ Bit 6

(LSB)

(MSB)

7[bit] Digital=>Analog

Bit 0 Bit 1 ââââ Bit 6

(LSB)

(MSB)

7[bit] Digital=>Analog

Figure 8. Shift Register and Data Latch for Dot-Correction

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