TLC5922 Datasheet, PDF (7/16 Pages) Texas Instruments – LED DRIVER

www.ti.com
PRINCIPLES OF OPERATION (continued)
where:
I_Max = the maximum programmable current of each output
DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)
n = 0, 1, 2 ... 15
TLC5922
SLVS486 – SEPTEMBER 2003
Forcing OFF the Constant Current Outputs
The BLANK input pin is used to disable all OUTx constant-current output terminals. When BLANK is a logic 1, all
OUTx are forced off, regardless of any other logic operations.
Internal Register Definitions
The TLC5922 has two separate serial data shift-registers and two separate data-latches. The first combination of
registers and latches controls the ON/OFF function of the output. These are referred to as the EN_REG registers
and EN_LATCHn latches, where n= 0,1...15 and specifies the output channel. There are 16 EN_REG registers
and 16 EN_LATCHn latches. Both are one bit each. Figure 7 shows how these are connected.
The second combination of registers and latches controls the dot-correction value for each output. These are
referred to as the DC_REG registers and DC_LATCHn latches, where n=0,1...15 and specifies the output
channel. There are 112 DC_REG data shift-registers (1 bit each) and 16 DC_LATCHn latches (seven bits each).
Figure 8 shows how these are connected.
All data to the TLC5922 comes from the SIN pin. The MODE pin determines whether the inputs and outputs of
the TLC5922 are connected to the ON/OFF logic or the dot-correction logic. When MODE is a logic 0, all data is
connected to the ON/OFF logic. When MODE is a logic 1, all data is connected to the dot-correction logic.
Each rising edge of the SCLK pin shifts the data in either the EN_REG or DC_REG registers. Each rising edge
of the XLAT pin transfers the data from the selected registers (either EN_REG or DC_REG) and latches it into
the selected latch (EN_LATCHn or DC_LATCHn).
Turning ON/OFF the Constant Current Outputs
The TLC5922 EN_LATCHn data-latches hold the ON/OFF information for each output. When the MODE input is
low, the processor can access both the EN_LATCHn and EN_REG registers. The 16 cascaded EN_REG shift
registers transfer ON/OFF data from SIN to SOUT output at each rising edge of the SCLK pin. XLAT is held low
when the ON/OFF data is clocked into the TLC5922. When all data is clocked in, the rising edge of the XLAT pin
transfers and latches the ON/OFF data into the EN_LATCHn latches. Each of the 16 EN_LATCHn data-latches
holds a 1 bit digital code that turns each of the 16 outputs on or off. The processor must clock in 16 bits of data
to fully program the ON/OFF setting for all 16 outputs. The ON/OFF data becomes valid on the OUTn outputs
when BLANK goes low.
During the XLAT=H(MODE=L), shift-register loads the LOD status of each 16 outputs (and the controller can
read the LOD status from SOUT). Note that incoming data from the controller is latched at XLAT↑(MODE=L),
and afterwards, the shift-register loads LOD status during XLAT=H(MODE=L).
7