SN74AUC16501 Datasheet, PDF (8/13 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74AUC16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES418 – DECEMBER 2002 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C_L
(see Note A)
R_L
R_L
2 × V_CC
S1
Open
GND
TEST
t_PLH/t_PHL
t_PLZ/t_PZL
t_PHZ/t_PZH
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S1
Open
2 × V_CC
GND
LOAD CIRCUIT
V_CC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
C_L
15 pF
15 pF
15 pF
30 pF
30 pF
R_L
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V_∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
Input
Timing Input
t_w
V_CC/2
V_CC/2
V_CC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
Data Input
V_CC/2
V_CC
0V
t_su
t_h
V_CC/2
V_CC/2
V_CC
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
V_CC/2
V_CC
V_CC/2
0V
t_PLH
Output
V_CC/2
t_PHL
V_CC/2
V_OH
V_OL
t_PHL
t_PLH
Output
V_CC/2
V_CC/2
V_OH
V_OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
V_CC/2
V_CC/2
Output
Waveform 1
S1 at 2 × V_CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t_PZL
t_PZH
V_CC/2
V_CC/2
t_PLZ
V_OL + V_∆
t_PHZ
V_OH − V_∆
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
V_CC
0V
V_CC
V_OL
V_OH
≈0 V
NOTES: A. C_L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t_PLZ and t_PHZ are the same as t_dis.
F. t_PZL and t_PZH are the same as t_en.
G. t_PLH and t_PHL are the same as t_pd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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