MSP430FE42XA Datasheet, PDF (8/44 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430FE42xA
MIXED SIGNAL MICROCONTROLLER
SLAS588 -- FEBRUARY 2008
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog
Flash memory
PC out-of-range (see Note 4)
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
NMIIFG (see Notes 1 and 3)
(Non)maskable
Oscillator fault
OFIFG (see Notes 1 and 3)
(Non)maskable
0FFFCh
14
Flash memory access violation ACCVIFG (see Notes 1 and 3)
(Non)maskable
ESP430
MBCTL_OUTxIFG,
MBCTL_INxIFG
(see Notes 1 and 2)
Maskable
0FFFAh
13
SD16
SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable
0FFF8h
12
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
UTXIFG0
Maskable
0FFF0h
8
0FFEEh
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG
(see Notes 1 and 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges (from 0600h to 0BFFh).
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