LP38841-ADJ_15 Datasheet, PDF (8/15 Pages) Texas Instruments – 0.8A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors

LP38841-ADJ
SNVS305C – FEBRUARY 2005 – REVISED APRIL 2013
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BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 5.5V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 3.8V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. The S/D pin must be actively terminated through a
pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
Heatsinking for the SO-8 package is accomplished by allowing heat to flow through the exposed DAP on the
bottom of the package into the copper on the PC board. The exposed DAP must be soldered down to a copper
plane to get good heat transfer. It can also be connected through thermal vias to internal copper planes. Since
the DAP is physically connected to the backside of the die, it must be held at ground potential. Under all possible
conditions, the junction temperature must be within the range specified under operating conditions.
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