DS90LV031ATM-NOPB Datasheet, PDF (8/19 Pages) Texas Instruments – DS90LV031A 3V LVDS Quad CMOS Differential Line Driver

DS90LV031A
SNLS020C – JULY 1999 – REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual (SNLA187), AN-808 (SNLA028), AN-1035 (SNOA355), AN-977 (SNLA166), AN-
971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 8. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as
close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver
into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The output
current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as
discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as
shown in Figure 8. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a
differential voltage of 350 mV across the 100Ω termination resistor which the receiver detects with a 250 mV
minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350
mV – 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, V_OS) with respect to ground as
shown in Figure 7. Note that the steady-state voltage (V_SS) peak-to-peak swing is twice the differential voltage
(V_OD) and is typically 700 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static I_CC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver
and is a step down replacement for the 5V DS90C031 Quad Driver.
Power Decoupling Recommendations
Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF
in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the
printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit
board.
PC Board considerations
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
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