DRV8832-Q1_15 Datasheet, PDF (8/18 Pages) Texas Instruments – LOW-VOLTAGE MOTOR DRIVER IC

DRV8832-Q1
SLVSBW9B – APRIL 2013 – REVISED JANUARY 2014
www.ti.com
The circuit monitors the voltage difference between the output pins and integrates it, to get an average DC
voltage value. This voltage is divided by 4 and compared to the VSET pin voltage. If the averaged output voltage
(divided by 4) is lower than VSET, the duty cycle of the PWM output is increased; if the averaged output voltage
(divided by 4) is higher than VSET, the duty cycle is decreased.
During PWM regulation, the H-bridge is enabled to drive current through the motor winding during the PWM on
time. This is shown in the diagram below as case 1. The current flow direction shown indicates the state when
IN1 is high and IN2 is low.
Note that if the programmed output voltage is greater than the supply voltage, the device will operate at 100%
duty cycle and the voltage regulation feature will be disabled. In this mode the device behaves as a conventional
H-bridge driver.
During the PWM off time, winding current is re-circulated by enabling both of the high-side FETs in the bridge.
This is shown as case 2 below.
VCC
2
1
OUT1
OUT2
Shown with
IN1=1, IN2=0
1 PWM on
2 PWM off
Figure 4. Voltage Regulation
Reference Output
The DRV8832-Q1 includes a reference voltage output that can be used to set the motor voltage. Typically for a
constant-speed application, VSET is driven from VREF through a resistor divider to provide a voltage equal to
1/4 the desired motor drive voltage.
For example, if VREF is connected directly to VSET, the voltage will be regulated at 5.14 V. If the desired motor
voltage is 3 V, VREF should be 0.75 V. This can be obtained with a voltage divider using 53 kΩ from VREF to
VSET, and 75 kΩ from VSET to GND.
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