CD54HC192_1 Datasheet, PDF (8/21 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

CD54/74HC192, CD54/74HC193, CD54/74HCT193
Test Circuits and Waveforms
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
P0
P1
PRESET DATA
P2
P3
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BCD SEVEN.
CLOCK UP
3. COUNT UP TO EIGHT, NINE,
TERMINAL COUNT UP, ZERO,
CLOCK DOWN
ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
Q₀
TERMINAL COUNT DOWN, NINE,
EIGHT AND SEVEN.
Q₁
OUTPUTS
Q₂
Q₃
TERMINAL COUNT UP
TERMINAL COUNT DOWN
0
7
89012
RESET PRESET
COUNT UP
10987
COUNT DOWN
FIGURE 1. ’HC192 SYNCHRONOUS DECADE COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
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