BQ34Z950 Datasheet, PDF (8/28 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION ENABLED WITH IMPEDANCE TRACK WITH OPTIONAL DQ INTERFACE

bq34z950
SLUSBF0A – APRIL 2013 – REVISED MAY 2013
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ELECTRICAL CHARACTERISTICS (continued)
Over-operating free-air temperature range (unless otherwise noted), T_A = –40°C to 85°C, V_(REG25) = 2.41 V to 2.59 V,
V_(BAT) = 14 V, C_(REG25) = 1 µF, C_(REG33) = 2.2 µF; typical values at T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V_(SCC)
V_(SCD)
t_da
t_pd
SCC detection threshold
voltage accuracy
SCD detection threshold
voltage accuracy
Delay time accuracy
Protection circuit
propagation delay
V_(SCC) = 50 mV (min)
V_(SCC) = 200 mV; RSNS = 0, 1
V_(SCC) = 475 mV (max)
V_(SCD) = –50 mV (min)
V_(SCD) = –200 mV; RSNS = 0, 1
V_(SCD) = –475 mV (max)
30
50
70
180
200
220
mV
428
475
523
–30
–50
–70
–180
–200
–220
mV
–428
–475
–523
±15.25
μs
50
μs
FET DRIVE CIRCUIT; T_A = 25°C (unless otherwise noted)
V_(DSGON) = V_(DSG) – V_(PACK);
V_(DSGON)
DSG pin output on voltage V_(GS) connected to 10 MΩ; DSG and CHG on;
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T_A = –40°C to 100°C
V_(CHGON) = V_(CHG) – V_(BAT);
V_(CHGON)
CHG pin output on voltage V_(GS) = 10 MΩ; DSG and CHG on;
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T_A = –40°C to 100°C
V_(DSGOFF)
DSG pin output off voltage V_(DSGOFF) = V_(DSG) – V_(PACK)
V_(CHGOFF)
CHG pin output off voltage V_(CHGOFF) = V_(CHG) – V_(BAT)
t_r
Rise time
C_L= 4700 pF
V_(CHG): V_(PACK) ≥ V_(PACK) + 4 V
V_(DSG): V_(BAT) ≥V_(BAT) + 4V
t_f
Fall time
C_L= 4700pF
V_(CHG): V_(PACK) + V_(CHGON) ≥ V_(PACK)+
1V
V_(DSG): VC1 + V_(DSGON) ≥ VC1 + 1 V
V_(ZVCHG)
ZVCHG clamp voltage
BAT = 4.5 V
3.3
LOGIC; T_A = –40°C to 100°C (unless otherwise noted)
ALERT
60
R_(PULLUP)
Internal pullup resistance
RESET
1
12
16
V
12
16
V
0.2
V
0.2
V
400
1000
μs
400
1000
40
200
μs
40
200
3.5
3.7
V
100
200
kΩ
3
6
V_OL
Logic low output voltage
level
LOGIC SMBC, SMBD, DQ, ALERT, DISP
ALERT
RESET; V_(BAT) = 7 V; V_(REG25) = 1.5 V; I_(RESET) = 200 μA
GPOD; I_(GPOD) = 50 μA
0.2
0.4
V
0.6
V_IH
V_IL
V_OH
V_OL
C_I
I_lkg
ADC ⁽²⁾
High-level input voltage
Low-level input voltage
Output voltage high⁽¹⁾
Low-level output voltage
Input capacitance
Input leakage current
I_L = –0.5 mA
DQ, ALERT, DISP; I_L = 7 mA;
2.0
V_REG25–0.5
5
V
0.8
V
V
0.4
V
pF
1
µA
Input voltage range
Conversion time
TS1, using Internal V_ref
–0.2
1
V
31.5
ms
Resolution (no missing
codes)
16
bits
Effective resolution
14
15
bits
Integral nonlinearity
±0.03
%FSR ⁽³⁾
Offset error⁽⁴⁾
Offset error drift⁽⁴⁾
Full-scale error⁽⁵⁾
T_A = 25°C to 85°C
140
2.5
±0.1%
250
18
±0.7%
µV
μV/°C
Full-scale error drift
50
PPM/°C
(1) RC[0:7] bus
(2) Unless otherwise specified, the specification limits are valid at all measurement speed modes.
(3) Full-scale reference
(4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference.
(5) Uncalibrated performance. This gain error can be eliminated with external calibration.
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