BQ24704 Datasheet, PDF (8/31 Pages) Texas Instruments – Low Cost, Host-Controlled Li-Ion and Li-Polymer Battery Charger With Low Iq

bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
7 V ≤ V_PVCC ≤ 24 V, 0°C < T_J < +125°C, typical values are at T_A = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
PWM LOW SIDE DRIVER (LODRV)
R_DS(on)
Low side driver turn-on resistance
Low side driver turn-off resistance
REGN = 6 V, tested at 100 mA
REGN = 6 V, tested at 100 mA
3
6
Ω
0.6 1.2
PWM DRIVERS TIMING
Driver Dead Time — Dead time when
switching between LODRV and HIDRV. No
load at LODRV and HIDRV
30
ns
PWM OSCILLATOR
F_SW
PWM switching frequency
V_{RAMP_HEIGHT} PWM ramp height
QUIESCENT CURRENT
As percentage of PVCC
240 300 360 kHz
6.6
%PVCC
I_{OFF_STATE}
Total off-state battery current from SRP,
SRN, BAT, VCC, BTST, PH, etc.
I_AC
Adapter quiescent current
INTERNAL SOFT START (8 steps to regulation current)
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 5 V, T_J = 85°C
V_BAT = 16.8 V, V_ACDET < 0.6 V,
V_PVCC > 5 V, T_J = 125°C
V_PVCC = 20 V, charge disabled
7
10
µA
7
11
1 1.5 mA
Soft start steps
8
step
Soft start step time
1.7
ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from when adapter is detected
to when the charger is allowed to turn
on
0.9 1.2 1.5
s
ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION)
I_SYN Accuracy
ISYNSET pin voltage
V_(SRP-SRN) = 5 mV
–20%
20%
1
V
V_ISYNSET
ISYNSET rising deglitch
ISYNSET falling deglitch
20
µs
640
µs
LOGIC IO PIN CHARACTERISTICS (CHGEN)
V_IN(LO)
Input low threshold voltage
V_IN(HI)
Input high threshold voltage
I_BIAS
Input bias current
LOGIC INPUT PIN CHARACTERISTICS (CELLS)
V_CHGEN = 0 to V_REGN
0.8 V
2.1
1 µA
V_IN(LO)
V_IN(MID)
Input low threshold voltage, 3 cells
Input mid threshold voltage, 2 cells
CELLS voltage falling edge
CELLS voltage rising for MIN,
CELLS voltage falling for MAX
0.5
0.8
1.8 V
V_IN(HI)
Input high threshold voltage, 4 cells
CELLS voltage rising
I_{BIAS_FLOAT}
Input bias float current for 2-cell selection V = 0 to V_REGN
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (DPMDET)
2.5
–1
1 µA
V_O(LO)
Output low saturation voltage
Delay, rising/falling
Sink Current = 5 mA
0.5 V
7
9
11 ms
8
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