BQ24704 Datasheet, PDF (24/31 Pages) Texas Instruments – Low Cost, Host-Controlled Li-Ion and Li-Polymer Battery Charger With Low Iq

bq24704
SLUS838 – MAY 2009........................................................................................................................................................................................................ www.ti.com
PCB Layout Design Guideline
1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the
power ground are connected only at the power pad.
3. The AC current-sense resistor must be connected to ACP (pin 4) and ACN (pin 3) with a Kelvin contact. The
area of this loop must be minimized. An additional 0.1 µF decoupling capacitor for ACN is required to further
reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as possible.
4. The charge-current sense resistor must be connected to SRP (pin 16), SRN (pin 15) with a Kelvin contact.
The area of this loop must be minimized. An additional 0.1µF decoupling capacitor for SRN is required to
further reduce the noise. The decoupling capacitors for these pins should be placed as close to the IC as
possible.
5. Decoupling capacitors for PVCC (pin 1), VREF (pin 8), REGN (pin 21) should be placed underneath the IC
(on the bottom layer) with the interconnections to the IC as short as possible.
6. Decoupling capacitors for BAT (pin 14), IADAPT (pin 12) must be placed close to the corresponding IC pins
with the interconnections to the IC as short as possible.
7. Decoupling capacitor CX for the charger input must be placed close to the Q4 drain and Q5 source.
Figure 33 shows the recommended component placement with trace and via locations. For the QFN information,
see the SCBA017 and SLUA271 documents.
(a) Top Layer
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(b) Bottom Layer
Figure 33. Layout Example
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