BQ20Z655DBTR-R1 Datasheet, PDF (8/25 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION

bq20z655-R1
SLUSAN9 – AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), T_A = –40°C to 85°C, V_(REG25) = 2.41 V to 2.59 V,
V_(BAT) = 14 V, C_(REG25) = 1 µF, C_(REG33) = 2.2 µF; typical values at T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
ΔV_(REG25TEMP)
ΔV_(REG25LINE)
ΔV_(REG25LOAD)
I_(REG25MAX)
Regulator output change with
temperature
Line regulation
Load regulation
Current limit
I_(REG25OUT) = 2 mA;
T_A = –40°C to 100°C
5.4 < VCC or BAT < 25 V;
I_(REG25OUT) = 2 mA
0.2 mA ≤ I_(REG25OUT) ≤ 2 mA
0.2 mA ≤ I_(REG25OUT) ≤ 16 mA
drawing current until
REG25 = 2 V to 0 V
±0.2
3
10
7
25
25
50
5
40
75
3.3V LDO; I_(REG25OUT) = 0 mA; T_A = 25°C (unless otherwise noted)
V_(REG33)
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I_(REG33OUT) ≤ 25 mA;
T_A = –40°C to 100°C
ΔV_(REG33TEMP)
Regulator output change with I_(REG33OUT) = 2 mA;
temperature
T_A = –40°C to 100°C
ΔV_(REG33LINE) Line regulation
5.4 < VCC or BAT < 25 V;
I_(REG33OUT) = 2 mA
ΔV_(REG33LOAD) Load regulation
0.2 mA ≤ I_(REG33OUT) ≤ 2 mA
0.2 mA ≤ I_(REG33OUT) ≤ 25 mA
I_(REG33MAX)
Current limit
drawing current until REG33 = 3 V
short REG33 to VSS, REG33 = 0 V
3
3.3
3.6
±0.2
3
10
7
17
40
100
25
100
145
12
65
THERMISTOR DRIVE
V_(TOUT)
R_DS(on)
Output voltage
TOUT pass element
resistance
I_(TOUT) = 0 mA; T_A = 25°C
I_(TOUT) = 1 mA; R_DS(on) = (V_(REG25) - V_(TOUT) )/ 1 mA; T_A
= –40°C to 100°C
V_(REG25)
50
100
LED OUTPUTS
V_OL
Output low voltage
LED1, LED2, LED3, LED4, LED5
0.4
VCELL+ HIGH VOLTAGE TRANSLATION
V_(VCELL+OUT)
V_(VCELL+REF)
V_(VCELL+PACK)
V_(VCELL+BAT)
CMMR
Translation output
Common mode rejection ratio
VC(n) - VC(n+1) = 0 V;
T_A = –40°C to 100°C
VC(n) - VC(n+1) = 4.5 V;
T_A = –40°C to 100°C
internal AFE reference voltage ;
T_A = –40°C to 100°C
Voltage at PACK pin;
T_A = –40°C to 100°C
Voltage at BAT pin;
T_A = –40°C to 100°C
VCELL+
0.950
0.975
1
0.275
0.3
0.375
0.965
0.975
0.985
0.98 ×
V_(PACK)/18
0.98 ×
V_(BAT)/18
40
V_(PACK)/18
V_(BAT)/18
1.02 ×
V_(PACK)/18
1.02 ×
V_(BAT)/18
K= {VCELL+ output (VC5=0 V; VC4=4.5 V) - VCELL+
output (VC5=0 V; VC4=0 V)}/4.5
0.147
0.150
0.153
K
Cell scale factor
K= {VCELL+ output (VC2=13.5 V; VC1=18 V) - VCELL+
output
0.147
0.150
0.153
(VC5=13.5 V; VC1=13.5 V)}/4.5
I_(VCELL+OUT)
Drive Current to VCELL+
capacitor
VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;
T_A = –40°C to 100°C
12
18
V_(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) - CELL output (VC2 =
VC1 = 0 V)
-18
-1
18
I_VCnL
VC(n) pin leakage current
CELL BALANCING
VC1, VC2, VC3, VC4, VC5 = 3 V
-1
0.01
1
R_BAL
internal cell balancing FET
resistance
R_DS(on) for internal FET switch at
V_DS = 2 V; T_A = 25°C
200
400
600
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; T_A = 25°C (unless otherwise noted)
V_(OL)
OL detection threshold
voltage accuracy
V_OL = 25 mV (min)
V_OL = 100 mV; RSNS = 0, 1
V_OL = 205 mV (max)
15
25
35
90
100
110
185
205
225
UNIT
%
mV
mV
mA
V
%
mV
mV
mA
V
Ω
V
V
dB
μA
mV
μA
Ω
mV
8
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