BQ20Z655DBTR-R1 Datasheet, PDF (2/25 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION

bq20z655-R1
SLUSAN9 – AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
bq20z655-R1
TSSOP
UNITS
θ_{JA, High K}
θ_JC(top)
θ_JB
ψ_JT
ψ_JB
θ_JC(bottom)
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter ⁽⁶⁾
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
44 PINS
60.9
15.3
30.2
0.3
27.2
n/a
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
SYSTEM PARTITIONING DIAGRAM
PACK+
DISP
LED Display
SMBD
SMBC
SMB 1.1
Data Flash
Memory
JEITA and
Enhanced
Charging
Algorithm
SHA-1
Authentication
Fuse Blow
Detection & Logic
Oscillator
System Control
Over
Temperature
Protection
Temperature
Measurement
Over & Under
Voltage
Protection
Over Current
Protection
PreCharge FET
& GPOD Drive
N Channel FET
Drive
Power Mode
Control
Voltage
Measurement
Impedance
Track™ Gas
Gauging
Coulomb
Counter
AFE HW Control
HW Over
Current & Short
Circuit Protection
Watchdog
Cell Voltage
Multiplexer
Cell Balancing
Regulators
RBI
MSRT
RESET
ALERT
VCELL+
VC1
VC2
VC3
VC4
VC5
REG33
REG25
+
VC1
+
VC2
VC3
+
VC4
VDD
OUT
CD
GND
+
bq294xx
PACK–
RSNS
5 mΩ – 20 mΩ typ
2
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