ADS5517 Datasheet, PDF (8/54 Pages) Texas Instruments – 11-BIT, 200 MSPS ADC

ADS5517
SLWS203 – DECEMBER 2007
www.ti.com
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
t_PDI
Clock propagation delay⁽⁷⁾
LVDS bit clock duty cycle
t_r ,
Data rise time,
t_f
Data fall time
t_CLKRISE, Output clock rise time,
t_CLKFALL Output clock fall time
Output clock jitter
t_OE
Output enable (OE) to valid data
delay
PARALLEL CMOS MODE
t_su
Data setup time ⁽⁵⁾
t_h
Data hold time ⁽⁵⁾
t_PDI
Clock propagation delay⁽⁷⁾
Output clock duty cycle
t_r ,
Data rise time,
t_f
Data fall time
t_CLKRISE, Output clock rise time,
t_CLKFALL Output clock fall time
t_OE
Output enable (OE) to valid data
delay
TEST CONDITIONS
Input clock rising edge zero-cross to output
clock rising edge zero-cross
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
80 ≤ Fs ≤ 200 MSPS
Rise time measured from –50 mV to 50
mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 200 MSPS
Rise time measured from –50 mV to 50
mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 200 MSPS
Cycle-to-cycle jitter
Time to valid data after OE becomes
active
Data valid⁽⁸⁾ to 50% of CLKOUT rising
edge
50% of CLKOUT rising edge to data
becoming invalid⁽⁸⁾
Input clock rising edge zero-cross to 50%
of CLKOUT rising edge
Duty cycle of output clock (CLKOUT)
80 ≤ Fs ≤ 200 MSPS
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 200 MSPS
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 200 MSPS
Time to valid data after OE becomes
active
MIN
3.7
45%
50
50
1.8
0.4
2.6
0.8
0.4
TYP
4.4
50%
MAX
5.1
UNIT
ns
55%
100
200 ps
100
120
2.6
0.8
3.4
45%
200 ps
ps pp
1 µs
ns
ns
4.2 ns
1.5
2.0 ns
0.8
1.2 ns
50 ns
(7) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (t_D) to get the desired setup and hold
times. Use either of these equations to calculate t_D:
Desired setup time = t_D - (t_PDI - t_su )
Desired hold time = (t_PDI + t_h ) - t_D
(8) Data valid refers to logic high of 2 V and logic low of 0.8 V
8
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