TMS320C5504_15 Datasheet, PDF (79/143 Pages) Texas Instruments – TMS320C5504 Fixed-Point Digital Signal Processor

TMS320C5504
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SPRS659G – AUGUST 2010 – REVISED SEPTEMBER 2013
5.7.4 Reset Electrical Data/Timing
Table 5-6. Timing Requirements for Reset⁽¹⁾ (see Figure 5-11)
NO.
CV_DD = 1.05 V
CV_DD = 1.3 V
CV_DD = 1.4 V _UNIT
MIN MAX MIN MAX MIN MAX
1 t_w(RSTL)
Pulse duration, RESET low
3P
3P
3P
ns
(1) P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator is
bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.
RESET
LOW Group
HIGH Group
Z Group
SYNCH X ® 0
Group
SYNCH X® 1
Group
SYNCH 0® 1
Group
SYNCH 1® 0
Group
CLKOUT
65536 + 38 clocks if CLK_SEL = 1,
32 + 38 clocks if CLK_SEL = 0
Figure 5-11. Reset Timing Requirements
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Peripheral Information and Electrical Specifications
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