TMS320C5504_15 Datasheet, PDF (17/143 Pages) Texas Instruments – TMS320C5504 Fixed-Point Digital Signal Processor

TMS320C5504
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2.5.1 Oscillator and PLL Terminal Functions
SPRS659G – AUGUST 2010 – REVISED SEPTEMBER 2013
Table 2-5. Oscillator and PLL Terminal Functions
SIGNAL
NAME
NO.
TYPE ⁽¹⁾
(2)
OTHER ^{(3) (4)}
DESCRIPTION
DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap
different clocks within the system clock generator. The SRC bits in the CLKOUT
Control Source Register (CCSSR) can be used to specify the CLKOUT pin source.
Additionally, the slew rate of the CLKOUT pin can be controlled by the Output
Slew Rate Control Register (OSRCR) [0x1C16].
CLKOUT
A7
O/Z
–
DV_DDIO
BH
The CLKOUT pin is enabled/disabled through the CLKOFF bit in the CPU ST3_55
register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At
reset the CLKOUT pin is enabled until the beginning of the boot sequence, when
the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z).
For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU
Reference Guide (literature number: SWPU073).
Note: This pin may consume static power if configured as Hi-Z and not pulled high
or low. Prevent current drain by externally terminating the pin.
Input clock. This signal is used to input an external clock when the 32-KHz on-chip
oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the
CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz.
CLKIN
A8
I
–
DV_DDIO
BH
The CLK_SEL pin (C7) selects between the 32-KHz crystal clock or CLKIN.
When the CLK_SEL pin is low, this pin should be tied to ground (V_SS). When
CLK_SEL is high, this pin should be driven by an external clock source.
If CLK_SEL is high, this pin is used as the reference clock for the clock generator
and during bootup the bootloader bypasses the PLL and assumes the CLKIN
frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. With
these frequencies in mind, the bootloader sets the SPI clock rates at 500 KHz and
the I2C clock rate at 400 KHz.
Clock input select. This pin selects between the 32-KHz crystal clock or CLKIN.
CLK_SEL
C7
I
–
DV_DDIO
BH
0 = 32-KHz on-chip oscillator drives the RTC timer and the system clock generator
while CLKIN is ignored.
1 = CLKIN drives the system clock generator and the 32-KHz on-chip oscillator
drives only the RTC timer.
This pin is not allowed to change during device operation; it must be tied high or
low at the board.
1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120
MHz).
V_{DDA_PLL}
C10
PWR
see Section 4.2, ^{This signal can be powered from the ANA_LDOO pin.}
ROC
1.4-V Analog PLL power supply for the system clock generator (PLLOUT > 120
MHz).
V_{SSA_PLL}
Note: When V_{DDA_PLL} requires 1.4V, V_{DDA_PLL} must be powered externally.
D9
GND
see Section 4.2,
ROC
Analog PLL ground for the system clock generator.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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