LM3S9B96 Datasheet, PDF (79/1282 Pages) Texas Instruments – Stellaris® LM3S9B96 Microcontroller

Figure 2-2. TPIU Block Diagram
Stellaris® LM3S9B96 Microcontroller
Debug
ATB
Slave
Port
ATB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
APB
Slave
Port
APB
Interface
2.2.5
2.2.6
2.2.7
ROM Table
The default ROM table is implemented as described in the ARM® Cortex™-M3 Technical Reference
Manual.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S9B96 controller and supports the
standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full
support for protection regions, overlapping protection regions, access permissions, and exporting
memory attributes to the system.
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
by enabling the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
June 14, 2010
79
Texas Instruments-Advance Information