LM3S9B96 Datasheet, PDF (313/1282 Pages) Texas Instruments – Stellaris® LM3S9B96 Microcontroller

Stellaris® LM3S9B96 Microcontroller
(see page 341) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 342) have been set.
9.2.5
Pad Control
The pad control registers allow software to configure the GPIO pads based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable
for each GPIO.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the V_OL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
9.2.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.3 Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the
Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris^® parts. The other
aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides
better back-to-back access performance than the APB bus. These apertures are mutually exclusive.
The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL
register (see page 135).
To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the
appropriate GPIO Port bit field (GPIOn) in the RCGC2 register (see page 193).
On reset, all GPIO pins are configured out of reset to be undriven (tristate): GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for the pins shown in Table 9-1 on page 305.
Table 9-4 on page 313 shows all possible configurations of the GPIO pads and the control register
settings required to achieve them. Table 9-5 on page 314 shows how a rising edge interrupt is
configured for pin 2 of a GPIO port.
Table 9-4. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
PUR
?
?
X
X
?
PDR
?
?
X
X
?
DR2R
X
?
?
?
X
DR4R
X
?
?
?
X
DR8R
X
?
?
?
X
SLR
X
?
?
?
X
June 14, 2010
313
Texas Instruments-Advance Information