TMS320VC5509 Datasheet, PDF (78/122 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.6.2 Layout Considerations
Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout
practices should always be observed when planning trace routing to the discrete components used in the
oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close
to the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible
after routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should
be run between these two signal lines. This also helps to minimize stray capacitance between these two
signals.
5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or
four to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock
mode register. The contents of this field only affect clock generation while the device is in bypass mode. In
this mode, the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−3 and Table 5−4 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5−3).
Table 5−3. CLKIN Timing Requirements
NO.
MIN MAX UNIT
C1 t_c(CI)
Cycle time, X2/CLKIN
20 400^† ns
C2 t_f(CI)
Fall time, X2/CLKIN
4 ns
C3 t_r(CI)
Rise time, X2/CLKIN
4 ns
C10 t_w(CIL)
Pulse duration, CLKIN low
6
ns
C11 t_w(CIH)
Pulse duration, CLKIN high
6
ns
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN cycle}
time is limited by the crystal frequency range listed in Table 5−2.
Table 5−4. CLKOUT Switching Characteristics
NO.
PARAMETER
MIN
TYP MAX UNIT
C4 t_c(CO)
Cycle time, CLKOUT
20^‡
D*t_c(CI)§ 1600^† ns
C5 t_d(CIH-CO) Delay time, X2/CLKIN high to CLKOUT high/low
10
20
30
ns
C6 t_f(CO)
Fall time, CLKOUT
1
ns
C7 t_r(CO)
Rise time, CLKOUT
1
ns
C8 t_w(COL)
Pulse duration, CLKOUT low
H−2
H+2 ns
C9 t_w(COH)
Pulse duration, CLKOUT high
H−2
H+2 ns
† _{This device utilizes a fully static design and therefore can operate with tc(CO) approaching ∞. If an external crystal is used, the X2/CLKIN cycle}
time is limited by the crystal frequency range listed in Table 5−2.
‡ _{It is recommended that the DPLL synthesised clocking option be used to obtain maximum operating frequency.}
§ _{D = 1/(PLL Bypass Divider)}
78 SPRS163G
April 2001 − Revised September 2004