TMS320VC5509 Datasheet, PDF (21/122 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z^†
FUNCTION
BK^‡
RESET
CONDITION
PARALLEL BUS (CONTINUED)
EMIF byte enable 0 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 0 control (EMIF.BE0) or HPI byte
C8
I/O/Z
identification (HPI.HBE0). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
EMIF.BE0
HPI.HBE0
Active-low EMIF byte enable 0 control. EMIF.BE0 is selected when the
O/Z Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
HPI byte identification. This pin, in conjunction with HPI.HBE1, identifies ^BK
the first or second byte of the transfer. HPI.HBE0 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
I
NOTE: As of Revision 3.1 of the silicon, the byte-enable function on the
HPI will no longer be supported. HPI.HBE0 and HPI.HBE1 must
be pulled down by external resistors or driven low by the host
processor.
GPIO0 = 1:
Output,
EMIF.BE0
GPIO0 = 0:
Input,
HPI.HBE0
EMIF byte enable 1 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 1 control (EMIF.BE1) or HPI byte
C9
I/O/Z
identification (HPI.HBE1). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
EMIF.BE1
Active-low EMIF byte enable 1 control. EMIF.BE1 is selected when the
O/Z Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
GPIO0 = 1:
Output,
EMIF.BE1
HPI.HBE1
HPI byte identification. This pin, in conjunction with HPI.HBE0, identifies ^BK
the first or second byte of the transfer. HPI.HBE1 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
I
NOTE: As of Revision 3.1 of the silicon, the byte-enable function on the
GPIO0 = 0:
Input,
HPI.HBE1
HPI will no longer be supported. HPI.HBE0 and HPI.HBE1 must
be pulled down by external resistors or driven low by the host
processor.
† _{I = Input, O = Output, S = Supply, Hi-Z = High-impedance}
‡ _{BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,}
PD = pulldown, H = hysteresis input buffer
April 2001 − Revised September 2004
SPRS163G
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