TMS320VC5470 Datasheet, PDF (77/93 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
High inactive state without delay; the McBSP transmits data on the falling edge of BCLKX and receives data
on the rising edge of BCLKR.
Table 6–24 and Table 6–25 assume testing over recommended operating conditions, CLKSTP = 10b,
CLKXP = 1, and H = 0.5t_c(CO) (see Figure 6–21).
NOTE: For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting
CLKSM = CLKGDV = 1.
Table 6–24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b and CLKXP = 1)
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
tsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV) Hold time, BDR valid after BCLKX high
12
– 12H
ns
0
12H + 5
ns
tsu(BFXL-BCKXL) Setup time, BFSX low before BCLKX low
10
ns
tc(BCKX)
Cycle time, BCLKX
12H
32H
ns
Table 6–25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b and CLKXP = 1)
PARAMETER
MASTER^†
MIN MAX
SLAVE
UNIT
MIN
MAX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
Hold time, BFSX low after BCLKX high^‡
Delay time, BFSX low to BCLKX low^§
T–6 T+6
ns
C–6 C+6
ns
td(BCKXL-BDXV)
Delay time, BCLKX low to BDX valid
–3
7 6H + 5 10H + 14 ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
D–2 D+3
ns
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from BFSX
high
2H + 3 6H + 17 ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
4H – 2 8H + 17 ns
† _{T = BCLKX period = (1 + CLKGDV) * 2H}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
‡ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
§ _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
LSB
BFSX
BDX
BDR
Bit 0
Bit 0
tsu(BFXL-BCKXL)
th(BCKXH-BFXL)
tdis(BFXH-BDXHZ)
tdis(BCKXH-BDXHZ)
tsu(BDRV-BCKXH)
MSB
tc(BCKX)
td(BFXL-BCKXL)
td(BFXL-BDXV)
td(BCKXL-BDXV)
Bit(n-1)
(n-2)
(n-3)
Bit(n-1)
th(BCKXH-BDRV)
(n-2)
(n-3)
(n-4)
(n-4)
Figure 6–21. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
December 2001 – Revised December 2002
SPRS017B
67