TMS320VC5470 Datasheet, PDF (10/93 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Tables
Table
6–20
6–21
6–22
6–23
6–24
6–25
6–26
6–27
6–28
6–29
6–30
6–31
6–32
6–33
6–34
6–35
6–36
6–37
6–38
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b and CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b and CLKXP = 0) . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b and CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b and CLKXP = 0) . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b and CLKXP = 1) . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b and CLKXP = 1) . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b and CLKXP = 1) . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b and CLKXP = 1) . . .
Synchronous DRAM Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous DRAM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C Bus Device Switching Characteristics of the SDA and SCL Bus Lines . . . . . . . . . . . . . . . . . . .
I²C Bus Device Timing Requirements (STOP and START Conditions) . . . . . . . . . . . . . . . . . . . . . .
I²C Bus Device Timing Requirements (Repeated START Condition) . . . . . . . . . . . . . . . . . . . . . . . .
ARM SRAM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARM SRAM Timing Requirements (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ARM SRAM Timing Requirements (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Clock Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Falling Edge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Rising Edge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
65
65
66
66
67
67
68
68
69
69
73
74
74
75
75
77
79
79
81
x
SPRS017B
December 2001 – Revised December 2002