PCI7610 Datasheet, PDF (77/240 Pages) Texas Instruments – PC Card, UltraMedia, and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller

4 PC Card Controller Programming Model
This chapter describes the PCI7610 PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI7610 function. There are some bits which affect both CardBus functions, but which, in order to work
properly, must be accessed only through function 0. These are called global bits. Registers containing one or more
global bits are denoted by § in Table 4−2.
Any bit followed by a † is not cleared by the assertion of PRST (see CardBus Bridge Power Management,
Section 3.9.10, for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only by
GRST. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to
as PME context bits and are implemented to allow PME context to be preserved during the transition from D3_hot or
D3_cold to D0.
If a bit is followed by a ‡, then this bit is cleared only by GRST in all cases (not conditional on PME being enabled).
These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm
resets.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
Table 4−1. Bit Field Access Tag Descriptions
ACCESS TAG
R
W
S
C
U
NAME
Read
Write
Set
Clear
Update
MEANING
Field can be read by software.
Field can be written by software to any value.
Field can be set by a write of 1. Writes of 0 have no effect.
Field can be cleared by a write of 1. Writes of 0 have no effect.
Field can be autonomously updated by the PCI7610 controller.
4.1 PCI Configuration Registers (Functions 0 and 1)
The PCI7610 controller is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and
1. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is
PC99/PC2001 compliant as well. Table 4−2 illustrates the PCI configuration register map, which includes both the
predefined portion of the configuration space and the user-definable registers.
Table 4−2. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME
Device ID
Vendor ID
Status ‡
Command
Class code
Revision ID
BIST
Header type
Latency timer
Cache line size
CardBus socket registers/ExCA base address register
Secondary status ‡
Reserved
Capability pointer
CardBus latency timer
Subordinate bus number
CardBus bus number
PCI bus number
CardBus memory base register 0
CardBus memory limit register 0
CardBus memory base register 1
CardBus memory limit register 1
‡ _{One or more bits in this register are cleared only by the assertion of GRST.}
OFFSET
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
4−1