PCI6515 Datasheet, PDF (77/148 Pages) Texas Instruments – SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET

Table 4−8. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
CardBus data parity SERR signaling enable.
4‡
CB_DPAR
RW
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
3‡
RSVD
R Reserved. This bit returns 0 when read.
ExCA power control bit.
2‡
EXCAPOWER
R
0 = Enables 3.3 V (default)
1 = Enables 5 V
Keep clock. When this bit is set, the PCI6515 controller follows the CLKRUN protocol to maintain the
system PCLK and the CCLK (CardBus clock). This bit is global to the PCI6515 functions.
0 = Allow system PCLK and CCLK clocks to stop (default)
1‡
KEEPCLK
RW
1 = Never allow system PCLK or CCLK clock to stop
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK.
In the PCI6515 controller, setting this bit maintains both the PCI clock and the CCLK.
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (R03).
When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed to the
PME/RI_OUT terminal. If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output
is placed in a high-impedance state. This terminal is encoded as:
0‡
RIMUX
RW
0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1.
(default)
1 = PME signal is routed to the PME/RI_OUT terminal of the PCI6515 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (PCI offset 91h, see Section 4.37) is
0, then the output on the PME/RI_OUT terminal is placed in a high-impedance state.
‡ _{One or more bits in this register are cleared only by the assertion of GRST.}
4−19