PCI6515 Datasheet, PDF (125/148 Pages) Texas Instruments – SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET

7 Smart Card Controller Programming Model
This section describes the internal PCI configuration registers used to program the PCI6515 Smart Card controller
interface. All registers are detailed in the same format: a brief description for each register is followed by the register
offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
The PCI6515 controller is a multifunction PCI device. The Smart Card controller core is integrated as PCI function
5. The function 5 configuration header is compliant with the PCI Local Bus Specification as a standard header.
Table 7−1 illustrates the configuration header that includes both the predefined portion of the configuration space and
the user-definable registers.
Table 7−1. Function 5 Configuration Register Map
REGISTER NAME
Device ID
Vendor ID
Status
Command
Class code
Revision ID
BIST
Header type
Latency timer
Cache line size
Smart Card base address
Reserved
Subsystem ID ‡
Subsystem vendor ID ‡
Reserved
Reserved
PCI power
management
capabilities pointer
Reserved
Maximum latency Minimum grant
Interrupt pin
Interrupt line
Reserved
Power management capabilities
Next item pointer
Capability ID
PM data
(Reserved)
PMCSR_BSE Power management control and status ‡
Reserved
General control ‡
Subsystem access
Smart Card Configuration 1 ‡
Reserved
‡ _{One or more bits in this register are cleared only by the assertion of GRST.}
OFFSET
00h
04h
08h
0Ch
10h
14h−28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
58h
60h−FCh
7−1