LMK04816BISQE Datasheet, PDF (76/123 Pages) Texas Instruments – LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK04816
SNAS597B – JULY 2012 – REVISED APRIL 2013
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8.12 REGISTER 14
8.12.1 LOS_TIMEOUT
This bit controls the amount of time in which no activity on a CLKin causes LOS (Loss-of-Signal) to be
asserted.
R14[31:30]
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
Table 8-53. LOS_TIMEOUT, 2 bits
Timeout
1200 ns, 420 kHz
206 ns, 2.5 MHz
52.9 ns, 10 MHz
23.7 ns, 22 MHz
8.12.2 EN_LOS
Enables the LOS (Loss-of-Signal) timeout control.
R14[28]
0
1
Table 8-54. EN_LOS
LOS
Disabled
Enabled
8.12.3 Status_CLKin1_TYPE
Sets the IO type of the Status_CLKin1 pin.
Table 8-55. Status_CLKin1_TYPE, 3 bits
R14[26:24]
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
Polarity
Input
Input /w pull-up resistor
Input /w pull-down resistor
Output (push-pull)
Output inverted (push-pull)
Output (open source)
Output (open drain)
8.12.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type
There are two input buffer types for the PLL1 reference clock inputs: either bipolar or CMOS. Bipolar is
recommended for differential inputs such as LVDS and LVPECL. CMOS is recommended for DC coupled
single ended inputs.
When using bipolar, CLKinX and CLKinX* input pins must be AC coupled when using a differential or
single ended input.
When using CMOS, CLKinX and CLKinX* input pins may be AC or DC coupled with a differential input.
When using CMOS in single ended mode, the unused clock input pin (CLKinX or CLKinX*) must be AC
grounded. The used clock input pin (CLKinX* or CLKinX) may be AC or DC coupled to the signal source.
The programming addresses table shows at what register and address the specified CLKinX_BUF_TYPE
bit is located.
The CLKinX_BUF_TYPE table shows the programming definition for these registers.
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General Programming Information
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