LMK04816BISQE Datasheet, PDF (103/123 Pages) Texas Instruments – LMK04816 Three Input Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK04816
www.ti.com
SNAS597B – JULY 2012 – REVISED APRIL 2013
A complete filled out table for use of CLKout0 as the qualifying clock is shown in Table 9-6. It was created
by entering a digital delay of 13.5 for 0 degree phase shift, then decrementing the digital delay down to the
minimum value of 4.5. Since this did not result in all the possible phase shifts, the digital delay was then
incremented from 13.5 to 14.0 to complete all possible phase shifts.
Digital delay
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
Table 9-6. Example Digital Delay Calculation
Calculated time shift
(ns)
-4.5
-4.25
-4.0
-3.75
-3.5
-3.25
-3.0
-2.75
-2.5
-2.25
-2.0
-1.75
-1.5
-1.25
-1.0
-0.75
-0.5
-0.25
0
0.25
0.5
Relative time shift to 200 MHz
(ns)
0.5
0.75
1.0
1.25
1.5
1.75
2.0
2.25
2.5
2.75
3.0
3.25
3.5
3.75
4.0
4.25
4.5
4.75
0
0.25
0.5
Phase shift of 200 MHz
(degrees)
36
54
72
90
108
126
144
162
180
198
216
234
252
270
288
306
324
342
0
18
36
Observe that the digital delay value of 4.5 and 14.5 will achieve the same relative time shift/phase delay.
However programming a digital delay of 14.5 will result in a clock off time for the synchronizing clock to
achieve the same phase time shift/phase delay.
Digital delay value is programmed as CLKoutX_Y_DDLY - (0.5 * CLKoutX_Y_HS). So to achieve a digital
delay of 13.5, program CLKoutX_Y_DDLY = 14 and CLKoutX_Y_HS = 1. To achieve a digital delay of 14,
program CLKoutX_Y_DDLY = 14 and CLKoutX_Y_HS = 0.
9.8 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*)
The LMK04816 family features supporting circuitry for a discretely implemented oscillator driving the
OSCin port pins. Figure 9-4 illustrates a reference design circuit for a crystal oscillator:
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