TVP5031 Datasheet, PDF (72/85 Pages) Texas Instruments – NTSC/PAL VIDEO DECODER

2.11.45 FIFO Control
Address
B6h
FIFO Control (R/W)
765
Reserved
4
CCD
Reset
3
Read in
Progress
2
RAM Test
1
TTX PHI Output Enable
0
FIFO Reset
FIFO Reset
When a 1 is written to this register bit, the FIFO is flushed. This is done by clearing the read
and write pointers to zero, clearing the Tx count to zero and clearing all status flags. This
bit is automatically cleared back to 0.
TTX PHI Output Enable A 1 in this register enables access to the teletext data in the FIFO through the parallel host
port and disables access from the output formatter. A 0 disables access from the parallel
host and enables access from the output formatter. The default value is one.
RAM TEST
Setting this bit high allows the micro to write data into the FIFO. In this mode, data from the
TXP is ignored. This allows the micro to test the RAM by writing and reading test patterns.
The default value is zero.
Read in Progress
This bit indicates that the first byte of a teletext transaction has been read, but the last byte
has not been read. This bit can be used to verify data alignment as it is read from the FIFO.
CCD Reset
When a 1 is written to this register bit, the closed caption register is reset. Also, the status
flag is cleared to 0. This bit is automatically cleared back to 0.
2.11.46 FIFO RAM Test
Address
B7h
FIFO RAM Test (W)
7
6
5
4
3
2
1
0
FIFO RAM test register provides diagnostic capability into the internal teletext FIFO. This register can be written
sequentially with a block of data. The data is read back using the Teletext FIFO data register at address B0h to verify
the correct operation of the FIFO.
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