TMS320C6211B Datasheet, PDF (70/83 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K − AUGUST 1998 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 38)
NO.
1
t_su(FRH-CKSH)
2
t_h(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
−150
−167
MIN MAX
4
4
UNIT
ns
ns
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
1
2
Figure 38. FSR Timing When GSYNC = 1
70
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443